The present invention relates to an apparatus for synchronizing a plurality of circuits, and more specifically for synchronizing a plurality of asynchronous circuits during testing operations.
In many computer systems, not all circuits are driven by the same clock. Computer systems comprising circuits driven by different clocks are referred to herein as asynchronous systems, and intrasystem data transfers between circuits which are driven by different clocks are asynchronous. The asynchronous nature of inter-circuit communications between circuits within a computer system which are driven by different clocks makes accurate testing of such asynchronous systems difficult.
Specifically, a testing operation generally comprises the steps of monitoring actual outputs of a tested circuit at predetermined times and comparing those actual outputs of the tested circuit with predetermined correct outputs. The tested circuit is considered faulty if the actual outputs do not substantially match the predetermined correct outputs. For such a testing operation to work, one must be able to predict exactly when a valid (non-faulty) circuit will produce particular outputs.
However, the time that an asynchronous system will produce a given output may vary since the timing of data transfers within the system between a circuit driven by one clock and a circuit driven by another clock may vary. The variance in the timing of such data transfers may result from, for example, a variance in testing temperature. A change in testing temperature may affect the transfer timing between different circuits in different ways, depending on the direction and magnitude of the temperature change and the internal characteristics of the circuits involved.
Another reason for such variance in timing of data transfers is that such transfers are often effected upon the coincidence of particular timing, or clock, signals in two asynchronous circuits; the required coincidence of two independent clock signals cannot be predicted with sufficient accuracy to sufficiently accurately compare actual outputs with predetermined outputs to reliably test a computer system.
That is, if, during testing, the outputs of an asynchronous system are checked at the wrong times, then a valid asynchronous system may fail a testing operation, or a faulty asynchronous system may pass a testing operation. Testing becomes even more difficult when the separately-clocked circuits of an asynchronous system reside on a single integrated circuit chip, since there is generally no convenient way to directly monitor a chip's internal data transfers.
Further, certain testing techniques, such as scan-testing and burn-in testing, are rendered difficult and inefficient when the circuit to be tested contains separately-clocked regions. Scan-testing consists of shifting data directly into a specific component of a system configured as an integrated circuit, clocking the circuit to shift data from a first component through a series of other components, and then shifting the data out of the system. The data shifted out is then compared to predicted output data. If the data shifted out does not substantially match the predicted output data, then the integrated circuit is considered faulty.
Paths within an integrated circuit which couple the series of components through which data is shifted during scan-testing are called scan paths. When an integrated circuit does not comprise a plurality of separately-clocked circuits, a relatively simple set of instructions can be used to perform data loading and data shifting required by the scan-testing process. However, in asynchronous systems the boundary between separately-clocked components effectively becomes a barrier to scan paths. This is because one cannot reliably predict whether data will be transferred between asynchronous components during any particular clock cycle.
Consequently, each respective asynchronous circuit or region, within a tested system must be scan-tested separately. As a result, each asynchronous circuit requires its own set of instructions for loading and shifting data, and such instruction sets are typically more complex than they would be for the loading and testing of data within a synchronous system where respective intrasystem circuits are driven by the same clock. In addition, the testing is less comprehensive in such asynchronous systems where respective asynchronous circuits are scan-tested separately, since each separately-clocked circuit is tested in isolation, rather than being tested in conjunction with other circuits with which a respective tested circuit normally operates.
During burn-in testing, a system to be tested is placed in a high-temperature environment and selected signals are applied to the system while the system is clocked. By thus "exercising" the components of the system at a high temperature, any marginal components in the system are forced to fail. Burn-in testing for asynchronous systems is difficult, since a plurality of clock signals must be applied to the tested system to effectively "exercise" the system. In addition, the propagation of signals within even a valid chip is unpredictable, since such signals must cross the asynchronous boundaries between the separately-clocked circuits on components.
An attempt has been made to accurately predict the generation of outputs in an asynchronous system by allowing a tester to phase shift or "skew" the signal of one of the clocks in the tested system. The signal of one clock is skewed in order to "tune" the output timing to the timing of the test mechanism which monitors the outputs. The altered timing of the skewed clock signal will alter the timing of the asynchronous data transfers between the circuit driven by the skewed clock signal and the other circuits in the tested system. The altered timing of the asynchronous data transfers will, in turn, alter the timing of the outputs generated by the asynchronous system. Under the assumption that a successful test operation will only result when the output generation is accurately synchronized with output monitoring, the skew of the clock signal is adjusted until the asynchronous system tests valid.
This signal-skewing technique has the disadvantage that, even when the tested system is valid, the skewing process is relatively time consuming. Further, if the tested system is faulty, then the tester may waste time trying to skew the clock signal timing to achieve a valid test result when such a result is impossible. Further, the signal-skewing technique does not overcome the problems involved in scan testing or burn-in testing an asynchronous system, as described above.
As is evident from the foregoing, it is clearly desirable to provide an apparatus that allows asynchronous systems to be accurately tested without a preliminary clock tuning process. It is further desirable to provide an apparatus that allows asynchronous systems to be accurately tested more quickly than is currently possible using the clock signal skewing process of the prior art. It is further desirable to provide an apparatus that allows asynchronous systems to be accurately scan tested. Finally, it is desirable to provide an apparatus that allows asynchronous systems to be accurately burn-in tested.